One of the critical building blocks of wireless system is the frequency synthesizer or PLL (Phase Lock Loop). The synthesizer generates the required LO (Local Oscillator) signals to perform the frequency translations. Depending on the frequency planning of the wireless system, the frequency of the LO can be comparable with RF frequencies. In UWB systems, for example, the required frequency of the LO can be as high as 6 GHz. This prescaler takes the high frequency output of a LO and divides the applied frequency to a lower value. The prescaler circuit becomes the weak link of the entire system if the prescaler fails to properly divide the applied frequency.
To understand the important aspect of the divider, let's us consider an RF IC manufacturing yield. Over the process variations of the manufacturing yield, the receiver gain, NF (Noise Figure), output transmitter power and linearity can vary considerably. Under these conditions, as long as the synthesizer is still in lock, the end user can still establish a communication link. However, the system may suffer a degradation in performance. Thus, the system can operate and function, although the system may operate poorly.
If the synthesizer performance degrades and does not lock at all over the entire process, then, the yield loss can be complete and total. There will be no parts available. Therefore, the goal of the typical system designer is to make sure the synthesizer does not become a limiting factor in the operation of the system. The critical part of the synthesizer that can limit the bandwidth over the process is the prescaler or divider. This is the circuit component that must operate at the highest frequency within the integrated circuit other than the circuit that generates the high frequency LO.
A typical synthesizer consists of a phase detector, a charge pump, a loop filter, a VCO (Voltage Controlled Oscillator), a prescaler, and programmable dividers. Since the phase detector, charge pump, loop filter, and programmable dividers occur after the prescaler or divider, these components always operated at lower frequencies. Thus, the prescaler or divider is the most critical block and needs to be as robust as possible to insure that it operates at high frequencies.
A typical design of a conventional prescaler consists of high-speed latches and flip flops designed using CML (Current Mode Logic) techniques. The designer will determine the required speed over worst case. Under these conditions, the designer will set the current within the circuit. The maximum output swing is determined by resistance (if a resistor load is used) and the bias current. In a well-designed circuit, the time constant at the falling edge is determined by the bias current and output capacitance of the CML logic. For the rising edge, the RC time constant (determined by the resistive load and output capacitance) should be fast enough to charge up the capacitance of the following stage. This eliminates the performance degradation due to device transconductance since the RC time constant determines the rise time. Dependent on the technology, the capacitance load can be made a design variable but typically remains somewhat fixed. This occurs because the device must be large enough to provide the gain at the operating frequency, but not so large that its capacitance slows the circuit down.
Thus, a need exists to allow for greater flexibility in the design of the prescaler to allow the prescaler to operate more realiably at higher frequencies. In addition, as pointed out above, the capacitive load and device size of the conventional design of the prescaler limits the design flexibility. The inventive technique described in this specification overcomes these and other shortcoming of the current conventional prescaler design.